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Preliminary
Rev. 1.1E '99.02.10
HD66421
HD66421
(RAM-Provided 160 Channel 4-Level Grey Scale Driver for Dot Matrix Graphics LCD)
Description The HD66421 drives and controls a dot matrix graphic LCD(Liquid Crystal Display) using a bit-mapped method. It provides a highly flexible display through its on-chip display RAM, in which each two bits of data can be used to turn on or off one dot on LCD panel with four-level grey scale. A single HD66421 can display a maximum of 160x100 dots using its powerful display control functions. It can display only eight lines out of one hundred lines. Features * Built-in bit-mapped display RAM: 30kbits (160 x 100 x 2 bits) * Grey scale display: PWM four-level grey scale can be selected from 32 levels * Grey scale memory management: Packed pixel * Monochrome display: two planes can be selected. One plane is displayed while the other plane is being written. * Partial display: Eight-lines data can be displayed in any place * An 80-system MPU interface * Power supply voltage for operation : 2.2V to 5.5V * Power supply voltage for LCD : 18 V max. * Selectable multiplex duty ratio: 1/8, 1/64, 1/80, 1/100 * LCD driving alternating cycle: 7, 11, 13 lines or flame * Built-in oscillator: external resister * Low power consumption: * Circuits for generating LCD driving voltage : Contrast control, Operational amplifier, and Resistive dividers * Internal resistive divider: programmable bias rate * 32-level programmable contrast control * Wide range of instructions reversible display, display on/off, vertical display scroll, blink, reversible address, read-modify-write mode * Package: TCP This function realize low power consumption because high voltage for driving LCD is not needed. An MPU can access HD66421 at any time, because the MPU operations are asynchronous with the HD66421's system clock and display operation. Its low-voltage operation at 2.2 to 5.5V and standby function provides low power -dissipation, making the HD66421 suitable for small portable device applications.
Ordering Information Type No. HD66421TB0 HCD66421BP Package TCP Die with gold bump
1
Preliminary
Pin Arrangement
Rev. 1.1E '99.02.10
HD66421
GND1 VLCD1 VCC1 V5O V4O V3O V2O V1O GREF IREFM IREFP VLCD2 VLCD3 VCC2 GND2 GND3 VCC3 OSC1 OSC2 OSC CO DCON CL1 FLM M M/S RES CS RS WR RD VCC4 GND4 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 VCC5 GND5 VCC6 VLCD4 GND6
COM100 COM99 COM98
COM51 SEG160 SEG159 SEG158
LCD drive signal output pins
SEG3 SEG2 SEG1 COM50 COM49 COM3 COM2 COM1 2
Note: This figure is not drawn to a scale
I/O,Power supply pins
Preliminary
Pad Arrangement
Chip size : 8.99 x 4.72 mm Coordinate : Pad center Origin : Chip Center Bump size : GND1, GND8, dummy A, dummy B Power, I/O (Pad No. 276 to 321) COM1 - 100, SEG1 - 160, dummy1 -12
Rev. 1.1E '99.02.10
HD66421
70 x 70 m 50 x 70 m 35 x 50 m
GND7 GND8 COM1 Type code HD66421
GND2
GND1 COM100
SEG24 dummyA dummy1 dummy12
SEG137 dummy8
Pad Location Coordinate
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PAD NAME COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 COM24 COM25 COM26 COM27 COM28 COM29 COM30 X -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 Y 1731 1681 1631 1581 1531 1481 1430 1380 1330 1280 1230 1180 1130 1080 1030 980 930 880 830 780 730 680 630 580 530 480 430 380 330 280 No. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 PAD NAME COM31 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 X -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 Y 230 179 129 79 29 -21 -71 -121 -171 -221 -271 -321 -371 -421 -471 -521 -571 -621 -671 -721 -798 -848 -898 -948 -998 -1049 -1099 -1149 -1199 -1249 No. 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 PAD NAME SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 dummy A dummy 1 dummy 2 dummy 3 dummy 4 dummy 5 dummy 6 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 X -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4217 -4029 -3907 -3827 -3619 -3497 -3419 -2822 -2772 -2722 -2672 -2622 -2572 -2522 -2472 -2422 Y -1299 -1349 -1399 -1449 -1499 -1549 -1599 -1649 -1699 -1749 -1799 -1849 -1899 -1949 -2082 -2082 -2082 -2082 -2082 -2075 -2075 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082
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Preliminary
Rev. 1.1E '99.02.10
HD66421
No. 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140
PAD NAME SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83
X -2372 -2322 -2272 -2222 -2172 -2121 -2071 -2021 -1971 -1921 -1871 -1821 -1771 -1721 -1671 -1621 -1571 -1521 -1471 -1421 -1371 -1321 -1271 -1221 -1171 -1121 -1071 -1021 -971 -921 -870 -820 -770 -720 -670 -620 -570 -520 -470 -420 -370 -320 -270 -220 -170 -120 -70 70 120 170
Y -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082
No. 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190
PAD NAME SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133
X 220 270 320 370 420 470 520 570 620 670 720 770 820 870 921 971 1021 1071 1121 1171 1221 1271 1321 1371 1421 1471 1521 1571 1621 1671 1721 1771 1821 1871 1921 1971 2021 2071 2121 2172 2222 2272 2322 2372 2422 2472 2522 2572 2622 2672
Y -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082 -2082
No. 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240
PAD NAME SEG134 SEG135 SEG136 dummy 7 dummy 8 dummy 9 dummy 10 dummy 11 dummy 12 dummy B SEG137 SEG138 SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66
X 2722 2772 2822 3419 3497 3619 3827 3907 4029 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217
Y -2082 -2082 -2082 -2075 -2075 -2082 -2082 -2082 -2082 -2082 -1949 -1899 -1849 -1799 -1749 -1699 -1649 -1599 -1549 -1499 -1449 -1399 -1349 -1299 -1249 -1199 -1149 -1099 -1049 -998 -948 -898 -848 -798 -721 -671 -621 -571 -521 -471 -421 -371 -321 -271 -221 -171 -121 -71 -21 29
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Preliminary
Rev. 1.1E '99.02.10
HD66421
No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 PAD NAME COM67 COM68 COM69 COM70 COM71 COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM80 COM81 COM82 COM83 COM84 COM85 COM86 COM87 COM88 COM89 COM90 COM91 COM92 COM93 COM94 COM95 COM96 COM97 COM98 COM99 COM100 GND1 GND2 VLCD1 Vcc1 V5O V4O V3O V2O V1O X 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4217 4091 3992 3912 3809 3729 3628 3548 3447 3367 3266 3186 3084 3004 2903 2823 Y 79 129 179 230 280 330 380 430 480 530 580 630 680 730 780 830 880 930 980 1030 1080 1130 1180 1230 1280 1330 1380 1430 1481 1531 1581 1631 1681 1731 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 No. 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 PAD NAME GREF IREFM IREFP VLCD2 VLCD3 Vcc2 GND3 GND4 Vcc3 OSC1 OSC2 OSC CO DCON CL1 FLM M M/S RES CS RS WR RD Vcc4 GND5 X 2722 2642 2541 2461 2360 2280 2179 2099 2009 1929 1830 1750 1647 1567 1494 1414 1316 1236 947 867 766 686 585 505 404 324 223 143 41 -39 -140 -220 -321 -401 -502 -582 -683 -763 -864 -944 -1045 -1125 -1226 -1306 -1407 -1487 -1587 -1667 -1770 -1850 Y 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 No. 309 310 311 312 313 314 315 316 317 318 319 320 321 322 PAD NAME DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Vcc5 GND6 Vcc6 VLCD4 GND7 GND8 X -1948 -2028 -2131 -2211 -2310 -2390 -2494 -2574 -2672 -2752 -2856 -2936 -3034 -3114 -3218 -3298 -3398 -3478 -3581 -3661 -3739 -3819 -3910 -3990 -4091 -4217 Y 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195 2195
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Preliminary
Rev. 1.1E '99.02.10
HD66421 Pin Description
Number Pin Name of Pins I/O Connected to - Power supply Vcc1-6, GND1-6 12 4 - Power supply VLCD1-4 5 - V1 to V5 of V1O, V2O, V3O,V4O, HD66421 V5O OSC 1 I, Oscillator OSC1,OSC2 2 I/O resister or external clock CO 1 O OSC of Slave HD66421 DCON 1 O External DC/DC convertor CL1 1 I/O CL1 of HD66421 FLM 1 I/O FLM of HD66421 M 1 I/O M of HD66421 M/S 1 I Vcc or GND 1 IRES 1 I MPU CS RS 1 I MPU Description Vcc: +2.2V to +5.5V, GND: 0V Power supply to LCD driving circuit Several levels of power to the LCD driving outputs. Master HD66421 outputs these levels to the slave HD66421. Must be connected to external resister when using R-C oscillation. When using an external clock, it must be input to the OSC terminal. Clock output Controls on/off switch of external DC/DC convertor Line clock Frame signal Converts LCD driving outputs to AC Specifies master/slave mode. Reset the LSI internally when drive low. Select the LSI, specifically internal registers (index and data registers) when driven low. Select one of the internal registers; select the index register when driven low and data registers when driven low. Inputs write strobe; allows a write access when driven low. Inputs read strobe; allows a read access when driven low. 8-bits three-state bidirectional data bus; transfer data between the HD66420 and MPU through this bus. Output column drive signals Output row drive signals Power supply for internal operation amplifier Bias current for internal operational amplifier Power supply for internal operation amplifier
WR RD DB7 to DB0 SEG1 to SEG160 COM1 to COM100 IREFP IREFM GREF
1 1 8 160 100 1 1 1
I I
MPU MPU
I/O MPU O LCD O LCD VCC External resistor GND
6
Preliminary
Register List
CS RS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Index Reg. Bits 4 3210 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 IR R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 Register Name R/W W W W W W R/W W W W W W W W W W W W W W 7 6
Rev. 1.1E '99.02.10
HD66421
Data bits 5 4 3
IR4 IR3
2
IR2
1
IR1
0
IR0 BLK
Index register Control register 1 Control register 2 X address register Y address register Display RAM access register Display start line register Blink start line register Blink end line register Blink register 1 Blink register 2 Blink register 3 Partial display block register Gray scale palette 1 (0,0) Gray scale palette 2 (0,1) Gray scale palette 3 (1,0) Gray scale palette 4 (1,1) Contrast control register Plane selection register Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
RMW DISP STBY PWR AMP REV HOLT ADC BIS1 BIS0 WLS GRAY DTY1 DTY0 INC XA5 XA4 XA3 XA2 XA1 XA0 YA6 YA5 YA4 YA3 YA2 YA1 YA0 D7 D6 ST6 D5 ST5 D4 ST4 D3 ST3 D2 ST2 D1 ST1 D0 ST0
BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0 BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0 BK0 BK1 BK2 BK3 BK4 BK5 BK6 BK7 BK8 BK9 BK10 BK11 BK12 BK13 BK14 BK15 BK16 BK17 BK18 BK19 CLE PB3 PB2 PB1 PB0 GP14 GP13 GP12 GP11 GP10 GP24 GP23 GP22 GP21 GP20 GP34 GP33 GP32 GP31 GP30 GP44 GP43 GP42 GP41 GP40 CM1 CM0 CC4 CC3 CC2 CC1 CC0 MON DSEL PSEL
7
Preliminary
RMW RMW = 1: Read-modify-write mode; Address is incremented only after write access RMW = 0: Address is incremented after both write and read access DISP DISP = 1: Display on DISP = 0: Display off STBY STBY = 1:Internal operation and power circuit halt; display off STBY = 0: Normal operation PWR PWR = 1: Output 'High' from DCON PWR = 0: Output 'Low' from DCON AMP AMP = 1: OP amp enable AMP = 0: OP amp disable REV REV = 1: Reverse display REV = 0: Normal display HOLT HOLT = 1: Internal operation stops, Oscillator works HOLT = 0: Internal operation starts ADC ADC = 1: Data in X address H'0 is output from SEG160 ADC = 0: Data in X address H'0 is output from SEG1 BIS1, 0 BIS1, 0 = (1,1): 1/8 LCD drive levels bias ratio BIS1, 0 = (1,0): 1/9 LCD drive levels bias ratio BIS1, 0 = (0,1): 1/10 LCD drive levels bias ratio BIS1, 0 = (0,0): 1/11 LCD drive levels bias ratio WLS WLS = 1: 6-bit data is valid WLS = 0: 8-bit data is valid GRAY GRAY = 1: Grayscale palette is available(gray scales can be selected from 32-levels) GRAY = 0: Grayscale palette is not available(4-gray scales fixed) DTY1, 0 DTY1, 0 = (1,1): 1/8 display duty cycle - Partial display DTY1, 0 = (1,0): 1/64 display duty cycle DTY1, 0 = (0,1): 1/80 display duty cycle DTY1, 0 = (0,0): 1/100 display duty cycle INC INC = 1: X address is incremented for each access INC = 0: Y address is incremented for each access
Rev. 1.1E '99.02.10
HD66421
8
Preliminary
BLK BLK = 1: Blink function is used BLK = 0: Blink function is not used CM1, 0 CM1, 0 = (1,1): Alternative cycle is 13 lines. CM1, 0 = (1,0): Alternative cycle is 11lines. CM1, 0 = (0,1): Alternative cycle is 7 lines. CM1, 0 = (0,0): Alternative cycle is 1 frame. MON MON = 1: Monochrome display MON = 0: Four levels gray scale display DSEL DSEL = 1: Plane 1 is displayed DSEL = 0: Plane 0 is displayed PSEL PSEL = 1: Plane 1 is read/written from the MPU PSEL = 0: Plane 0 is read/written from the MPU CLE CLE = 1: CO,CL1,FLM,M stop in master mode. They are high-Z. CLE = 0: CO,CL1,FLM,M are operating in master mode. Normal operation.
Rev. 1.1E '99.02.10
HD66421
9
Preliminary
Block Diagram
Rev. 1.1E '99.02.10
HD66421
COM1
COM50 SEG1
SEG160COM51
COM100
Row Driver Level Shifter
Column Driver Level Shifter
160
Row Driver Level Shifter
Attribute Grey scale selector
320
Comparator Row Counter
Data Latch2
320
Decoder
Data Latch1
320
320 x 80bit Display memory X Decoder Data Buffer X Address Counter Y Address Counter Blink Registers Start Line Register Blink Start Line Register Blink End Line Register Control Register Contrast Control Register
Y Decoder
Display Line Counter
Grey scale palette Grey scale pattern Generator
MPX
Timing Generator MPU Interface LCD driver power supply, Contrast control I/O control Oscillator
DB7 -DB0
RS
WR RD
CS M/S
V1O V3O V5O VLCD V2O V4O
FLM M CL1 DCON
RES OSC OSC2 OSC1 CO
5
10
Preliminary
System Description The HD66421 can display a maximum of 160 x 100 dots (ten 16x16-dot characters x 6 lines) four-level gray scale or four colour LCD panel. Four levels of gray scale can be selected from 32-levels, so the appropriate 4-level gray scale can be displayed. And Monochrome display can be selected from two planes. One plane is displayed
Rev. 1.1E '99.02.10
HD66421
while the other plane is being written. The HD66421 can reduce power dissipation without affecting display because data is retained in the display RAM even during standby modes. An LCD system can be configured simply by attaching external power supply, capacitors and resistors (figure 1) since the HD66421 incorporates power circuits.
LCD panel COM1 to COM50 SEG1 to SEG160 CS RS RD WR DB7 to DB0 8
COM51 to COM100
MPU
HD66421
DC/DC Convertor
Figure 1 System Block Diagram
11
Preliminary
MPU Interface The HD66421 can interface directly to an MPU through an 8-bit data bus or through an I/O port (figure 2). The MPU can access the HD66421 internal registers independently of internal clock timing. The index register can be directly accessed but the
Rev. 1.1E '99.02.10
HD66421
other registers (data registers) cannot. Before accessing a data register, its register number must be written to the index register. Once written, the register number is held until it is rewritten, enabling the same register to be consecutively accessed without having to rewrite to the register number for each access. An example of a register access sequence is shown in figure 3.
A15 - A0
decoder
CS RS RD HD66421 WR DB0 - DB7
Z80
A0 RD WR D0 - D7
8
a) Interface through Bus
H8/325
C0 C1 C2 C3
CS RS RD WR
HD66421
8
A0 - A7 DB0 - DB7
b) Interface through I/O Port
Figure 2 8-Bit MPU Interface Examples
CS RS WR RD DB7 to DB0 Data Write index register Data Write data register Data Write data register Data Write index register Data Read data register Data Read data register
Figure 3 8-Bit Data Transfer Sequence
12
Preliminary
LCD Driver Configuration Row and column outputs: The HD66421's row outputs is only both sides. In any case, each output's function is fixed; COM1 to COM100 output row signals and SEG1 to SEG160 output column signals.
Rev. 1.1E '99.02.10
HD66421
Dot-matrix Display
Row outputs from both sides of LCD 50-channel row output COM51 to COM100
160 x 100
50-channel row output COM1 to COM50
160-channel column output SEG1 to SEG160
HD66421
Figure 4 Common outputs from both sides
13
Preliminary
Column Address Inversion According to LCD Driver Layout: The HD66421 can always display data in address H'0 on the top left of an LCD panel regardless of where it is positioned with respect to the panel. This is because the HD66421 can invert the positional relationship between display RAM addresses and LCD driver output pins by inverting RAM addresses. Specifically, the HD66421 outputs data in address H'0 from SEG1 when the ADC bit in
Rev. 1.1E '99.02.10
HD66421
control register 1 is 0, and from SEG160 otherwise. Here. the scan direction of row output is also inverted according to the situation. as shown in figure 6. Note that addresses and scan direction are inverted when data is written to the display RAM, and thus changing the ADC bit after data has been written has no effect. Therefore. hardware control bits such as ADC must be set immediately after reset is canceled, and must not be set while data is being displayed.
COM1
H'0 H'1
HD66421 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 SEG1 SEG2 SEG3
COM50 LCD panel
COM100 COM51
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
H'0 H'1
SEG160 SEG159 SEG158
COM51 COM100
LCD panel
COM50 COM1
HD66421 a) ADC = 0 b) ADC = 1
Figure 5 LCD Driver Layout and RAM addresses : 1/100 Duty cycle
Table 1 Scanning Direction and RAM Address
DTY1 DTY0 0 0 ADC 0 1 0 1 0 1 0 1 0 1 0 1 1 1 COMMON COM1 -> COM50, COM100 -> COM51 COM51 -> COM100, COM50 -> COM1 COM1 -> COM40, COM100 -> COM61 COM61 -> COM100, COM40 -> COM1 COM1 -> COM32, COM100 -> COM69 COM69-> COM100, COM32 -> COM1 8 COM depend on R11 8 COM depend on R11 SEGMENT H'00 -> SEG1 H'00 -> SEG160 H'00 -> SEG1 H'00 -> SEG160 H'00 -> SEG1 H'00 -> SEG160 H'00 -> SEG1 H'00 -> SEG160
14
Preliminary
Multi-LSI Operation Using multiple HD66421s provides the means for extending the number of display dots. Note the following items when using the multi-LSI operation. (1) The master LSI and the slave LSI must be determined; the M/S pin of the master LSI must be set high and the M/S pin of the slave LSI must be set low. 2) The master LSI supplies the FLM, M, CL1 and clock signals to the slave LSI via the corresponding pins, which synchronizes the slave LSI with the master LSI. (3) All control bits of slave LSI must be set with the same data with that of the master LSI.
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HD66421
(4) All LSIs must be set to LCD off in order to turn off the display. (5) The standby function of slave LSI must be started up first, and that of the master LSI must be terminated first. (6) The power supply circuit of slave LSI stop working, so V1 to V5 levels are supplied from the master LSI. If the internal power supply circuit can not drive two LSIs, use an external power supply circuit. Figure 6 shows the configuration using two HD66421s and table 2 lists the differences between master and slave modes.
Dot-matrix Display
50-channel row output 160-channel column output HD66421 (Master)
M FLM
320 x 100
160-channel column output V1O to V5O
M FLM
50-channel row output
VCC M/S
V1O to V5O
CL1
HD66421 (slave)
M/S
OSC OSC1 CO
CL1 CO OSC1 OSC
Open
Figure 6 Configuration Using Two HD66421s Table 2 Comparison between Master and Slave Modes
Item Pin M/S OSC CO FLM, M, CL1 Registers R0, R2 to R15,R17 Master Mode Must be set high Oscillation is active Output Output signals Valid Valid Valid Valid Valid Slave Mode Must be set low Oscillation is active High-Z Input signals Valid Invalid Valid Invalid Invalid
R1:BIS1, 0 R1:other R16 Power supply circuit
15
Preliminary
Display RAM Configuration and Display The HD66421 incorporates a bit-mapped display RAM. It has 320 bits in the X direction and 100 bits in the Y direction. The 320 bits are divided into forty 8-bit groups. As shown in figure 7, data written by the MPU is stored horizontally with the MSB at the far left and the LSB at the far right. The consecutive two bits control one pixel of LCD in 4-level gray scale mode, this means that one 8-bits data contains data which controls four pixels. One bit of memory designates one dot of display in the monochrome display mode.
Rev. 1.1E '99.02.10
HD66421
The ADC bit of control register 1 can control the positional relationship between X addresses of the RAM and LCD driver output (figure 8). Specifically. the data in address H'0 is output from SEG1 when the ADC bit in control register 1 is 0, and from SEG160 otherwise. Here. data in each 8-bit group is also inverted. Because of this function, the data in X address H'0 can be always displayed on the top left of an LCD panel with the MSB at the far left regardless of the LSI is positioned with respect to the panel. In this case, DB7, DB5, DB3 and DB1 are more significant bit in consecutive two bits.
LCD panel
LCD panel
SEG1 SEG3 SEG2 SEG4 Y0 Y1 1 0 D B 7 1 0 D B 6 1 0 D B 5 0 1 D B 4 0 1 D B 3 1 0 D B 2 0 1 D B 1 0 1 D B 0
SEG157 SEG160 SEG1 1 0 D B 1
DEG159 SEG160 1 0 D B 4 0 1 D B 7 0 Y0 1 Y1 D B 6
SEG158 1 0 D B 0 1 0 D B 3 0 1 D B 2 0 1 D B 5
Display RAM
Display RAM
(a) MON = 0, ADC = 0, WLS= 0
(b) MON = 0, ADC = 1 , WLS= 0
Figure 7 Display RAM Data and Display in Gray Scale Mode
SEG1
LCD drive signal output
SEG160
SEG1
LCD drive signal output
SEG160
H'00 H'01 Y address
H'00 H'01 Y address H'62 H'63 H'0 MSB (a) MON = 0, ADC = 0, WLS= 0 H'1 X addresses H'27 H'27 MSB (b) MON = 0, ADC = 1, WLS= 0 H'26 X addresses H'0
H'62 H'63
Figure 8 Display RAM Configuration in Gray Scale Mode
16
Preliminary
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HD66421
LCD panel
LCD panel
SEG160 SEG159 SEG158 SEG157 SEG156 SEG155 SEG154 SEG153
SEG160
Y0 1 Y1 0 D B 7
H'00 H'01 Y address
H'62 H'63 H'0 MSB (a) MON = 1, ADC = 0 H'2 X address H'26
H'62 H'63 H'26 MSB (b) MON = 1, ADC = 1 H'24 X address H'0
Figure 10 Display RAM Configuration in Monochrome Mode
17
Y address
SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 1 0 D B 6 1 0 D B 5 0 1 D B 4 0 1 D B 3 1 0 D B 2 0 1 D B 1 0 1 D B 0
SEG1
Display RAM
Display RAM
1 0 D B 0
1 0 D B 1
1 0 D B 2
0 1 D B 3
0 1 D B 4
1 0 D B 5
0 1 D B 6
0 Y0 1 Y1 D B 7
(a) MON = 1, ADC = 0, WLS= 0
(b) MON = 1, ADC = 1, WLS= 0
Figure 9 Display RAM Data and Display in Monochrome Mode
SEG1
LCD drive signal output
SEG160
SEG1
LCD drive signal output
SEG160
H'00 H'01
Preliminary
Word Length The HD66421 can handle either 8- or 6-bits as a word. In the display memory, one X address is assigned to each word of 8- or 6-bits long in X direction.
SEG1
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HD66421
When the 6-bits mode is selected, only data on DB5 to DB0 are used and data on DB7 and DB6 are discarded. This word length is only applied to data to internal RAM. The word length of internal register is always 8-bits
LCD drive signal output
SEG160
SEG1
LCD drive signal output
SEG160
H'00 H'01 Y address
8 bits
H'00 H'01 Y address H'62 H'63 H'0 MSB (a) Address assignment when one word is 8 bits long (MON=0) H'1 X addresses MSB (b) Address assignment when one word is 6 bits long (MON=0) H'27 H'0 H'1 X addresses H'34 H'35 H'35
1 0 D B 3 0 1 D B 2 0 1 D B 1 1 0 D Display RAM B 0 1 0 D B 0 0 1 D B 5 0 1 D B 4 Y0 6 bits
H'62 H'63
Figure 11 Display RAM Addresses in Gray Scale Mode
H'0
Y0 1 Y1 0 D B 5 1 0 D B 4
H'35
1 Y1 0 D B 1 1 0 D B 0 1 0 D B 3 0 1 D B 2 0 1 D B 5 1 0 D Display RAM B 4 1 0 D B 4
H'0
0 1 D B 1 0 1 D B 0
(a) WLS= 1, ADC = 0, MON= 0 H'35's bit7,6, and 3 to 0 are disable . H'0
1 0 D B 4 1 0 D B 3 0 1 D B 2 0 1 D B 1 1 0 D Display RAM B 0 0 1 D B 0 0 1 D B 5 1 0 D B 4
(b) WLS= 1, ADC = 1 MON= 0 H'0's bit7 to 2 are disable. H'34
Y0 1 Y1 0 D B 0 1 0 D B 1 1 0 D B 2 0 1 D B 3 0 1 D B 4 1 0 D Display RAM B 5 0 1 D B 5 0 1 D B 0 1 0 D B 1
Y0
H'34
0 1 D B 3 0 1 D B 2
H'0
0 1 D B 2 0 1 D B 3
1 Y1 0 D B 5
(c) WLS= 1, ADC = 0, MON= 1 H'34's bit7,6, and 1,0 are disable .
(d) WLS= 1, ADC = 1, MON= 1 H'0's bit7 to 4 are disable.
Figure 12 Display RAM Bits Map at 6-bits Mode
18
Preliminary
Monochrome Display Mode The HD66421 can control monochrome display. This mode is set when MON is set to 1. Two plane of display can be selected in this mode using two bits data for gray scale. One plane can be selected with PSEL bit for access from the CPU and with DSEL bit for display. Theses two operations are independent to each other, thus oneplane can be rewritten while the other plane is
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HD66421
displayed. This means no flicker during being rewritten. The address area is mapped to even address from H'0 to H'26 in monochrome mode and this address area is the same for both planes. The plane 0 is accessed when PSEL is cleared to 0 and the plane 1 is selected when PSEL is set to 1. The plane 0 is displayed when DSEL is cleared to 0 and the plane 1 is displayed when DSEL is set to 1.
DSEL plane 1 plane 0
PSEL
Figure 13 Memory Planes in Monochrome Display Mode
SEG1
LCD drive signal output
SEG160
H'00 H'01 Y address H'62 H'63 H'0 H'2 H'26
Figure 14 Memory Addresses in Monochrome Display Mode
19
Preliminary
Configuration of Display Data Bit Packed Pixel Method For grey scale display and super reflective colour display, multiple bits are needed for one pixel. In the HD66421, two bits are assigned to one pixel, enabling a four-level grey scale display and four colour display. One address, eight bits, specifies four pixels, and pixel bits 0 and 1 for gray scale are managed as consecutive bits in one byte.
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When grey scale display data is manipulated in bit units, one memory access is sufficient, which enables smooth high-speed data rewriting. The bit data to input to pin DB7, DB5, DB3 and DB1 become MSB and the bit data to input via pin DB6, DB4, DB2 and DB0 are LSB.
LCD display state Grey scale/colour palette
FRC control circuit
00011011 Bit 76543210 4 pixels/address Address: n
00001010 76543210 Address: n + 1
Physical memory
Figure 15 Packed Pixel Method Gray scale/Colour palette The HD66421 uses PWM, Pulse Width Modulation, technique for gray scale display. A period of one line is divided into thirty-one or four and HD66421 outputs turn-on levels for one period and turn-off levels for rest of these period. This technique changes gray scale on monochrome display and colour on super reflective colour panel. The characteristics of these panel vary with different panel. To allow for this, the HD66421 designed to generate 32-levels gray scale levels and provides palette registers that assign desired levels to certain of the four colours, GRAY = 0, or generate dedicated 4-level grayscale , GRAY = 1. Using the palette registers to select any 4 out of 32 levels of applied voltages enables an optimal grayscale/colour display. Because of this grayscale technique using 32-levels gray scale needs higher clock rate. If 32-levels gray scale is not needed, lower clock rate can be used. Table 3 shows default value of palette registers and Table 4 and 5 show relationship between value of a palette register and grayscale level.
Table 3 Default Value of Palette Registers
DB7, 5, 3, 1 DB6, 4, 2, 0 0 0 1 1 0 1 0 1 Register Name Grayscale Palette 1 Grayscale Palette 2 Grayscale Palette 3 Grayscale Palette 4 0 0 1 1 Default Value 0 1 0 1 0 0 1 1 0 1 1 1 0 1 1 1
20
Preliminary
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HD66421
Table 4 Value of a Palette Register and Grayscale Levels (GRAY= 0)
Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Grayscale Level 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 1 default R12
default R13
default R14
default R15
Table 5 Grayscale Levels (GRAY= 1)
DB7,5,3,1 0 0 1 1 DB6,4,2,0 0 1 0 1 Grayscale Level 0 1/3 2/3 1
21
Preliminary
Access to Internal Registers and Display RAM Access to Internal Registers by the MPU: The internal registers includes the index register and data registers. The index register can be accessed by driving both the CS and RS signals low. To access a data register, first write its register number ID to the index register with RS set to 0, and then access the data register with RS set to 1 . Once written, the register number is held until it is rewritten, enabling the same register to be consecutively accessed without having to rewrite to the register number for each access. Some data registers contain unused bits; they should be set to 0. Note that all data registers except the display memory access register can only be written to. Access to Display RAM by the MPU: To access the display RAM, first write the RAM address desired to the X address register (R2) and the Y address register (R3). Then read/write the display memory access register (R4). Memory access by the MPU is independent of memory read by the HD66421 and is also asynchronous with the HD66421's clock, thus enabling an interface independent of HD66421's internal operations.
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HD66421
However, when reading. data is temporarily latched into a H66421's buffer and then output next time, a read is performed in a subsequent cycle. This means that a dummy read is necessary after setting X and Y addresses. The memory read sequence is shown in figure 16. X and Y addresses are automatically incremented after each memory access according to the INC bit value in control register 2; therefore, it is not necessary to update the addresses for each access. Figure 16 shows two cases of incrementing display RAM address. When the INC bit is 0, the Y address will be incremented up to H'7F with the X address unchanged. However, actual memory is valid only within H'00 to H'4F; accessing an invalid address is ignored. When the INC bit is 1 , the X address will be incremented up to H'27 or H'35 according to WLS bit with the Y address unchanged. After address H'27 or H'35, the X address will be returned to H'00; accessing more than forty bytes causes rewriting to the same address.
RS WR RD Input data Output data Address [*,*] [n,*] H'02 X Address [n] H'03 Y Address [m] H'04
Undetermined Data[n,m] Data[n,m+1] [n,m+2]
[n,m] Dummy read
[n,m+1]
Figure 16 Display RAM read sequence
22
Preliminary
Display RAM Reading by LCD Controller: Data is read by the HD66421 to be displayed asynchronously with accesses by the MPU. However, because simultaneous access could damaging data in the display RAM, the HD66421 internally arbitrates access timing; access by the
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HD66421
MPU usually has priority and so access by the HD66421 is placed between accesses by the MPU. Accordingly, an appropriate time must be secured (see the given electrical characteristics between two accesses by the MPU).
H'0 H'00 H'01
H'1
H'27
H'28
H'35
Valid area H'63
Invalid area
Valid area (WLS= 1)
Invalid area
H'7F WLS= 0 WLS= 1
(a) INC = 0
H'0 H'00 H'01 H'02 H'63 WLS= 0 WLS= 1 H'1 WLS= 0 H'27 H'28 WLS= 1 H'35
(b) INC = 1, MON= 0
H'0 H'00 H'01 H'02 H'63 WLS= 0 WLS= 1 H'2 WLS= 0 H'26 H'28 WLS= 1 H'34
(c) INC = 1, MON= 1 Figure 17 Display Address Increment
23
Preliminary
Read-Modify-Write: X- or Y-address is incremented after reading form or writing data to the display RAM at normal mode. However, Xor Y-address is not incremented after reading data from the display RAM at read-modify-write mode. The data which is read from the display RAM may be modified and written to the same
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HD66421
address without re-setting the address. Data is temporarily latched into a HD66421's buffer and then output next time a read is performed in a subsequent cycle. This means that the dummy read is necessary after every cycle. This sequence is shown in figure 18.
START
Set X-address
Set Y-address
dummy read
Read Data Address incremented
Write Data
Finish Modifying yes END
no
Figure 18 The Flow Chart for Read-Modify-Write
24
Preliminary
Arbitration Control The HD66421 controls the arbitration between draw access and display access. The draw access read and write display data of display memory incorporated in the HD66421. The display access outputs display data to the liquid crystal panel. The draw access has the priority over display access, so continuous access is enabled without having the system to wait. For arbitration control, draw access is recognized as valid when CS and WR/RD are low.
Rev. 1.1E '99.02.10
HD66421
When draw and display access occur at the same time, draw access is executed prior to display access. Display access is executed between two draw access during display access period. If a period of one draw access is longer than that of display access, display access will not be executed properly. If this condition happens frequently, flicker will be seen on the display. The low level width of WR and RD must be less than the period of display access - 450ns.
CS WR RD Draw access Display access period Draw access
Figure 19 Definition of Draw Access
Display Access Period WR CS Memory Access
period of 4 clocks (22s approx ) *
* In the case of fOSC = 180kHz
Draw Access
Display Access
Figure 20 Memory Access when Display and Draw Access Occur at The Same Time
Display Access Period WR CS Memory Access
period of 4 clocks (22us approx. ) * period of 4 clocks - 450ns
Draw Access Display Access (min. 450ns)
* In the case of fOSC = 180kHz
Figure 21 WR Low Level Width
25
Preliminary
Vertical Scroll Function The HD66421 can vertically scroll a display by varying the top raster to be displayed. which is specified by the display start raster register. Figure 22 and 23 show vertical scroll examples. As shown, when the top raster to be displayed is set to
Y-address H'00 H'01 H'02 H'03 H'04 H'05 H'06 H'07 H'08 H'09 H'0A H'60 H'61 H'62 H'63 Y-address H'01 H'02 H'03 H'04 H'05 H'06 H'07 H'08 H'09 H'0A H'0B
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HD66421
l, data in Y address H'0 is displayed on the 100th raster. To display another frame on the 100th raster, therefore, data in Y address H'0 must be modified after setting the top raster. When display duty is less than 100, for example 1/80, data of address H'50 is displayed after address H'4F.
Top raster to be displayed = 0
Top raster to be displayed = 1
H'61 H'62 H'63 H'00 Y-address H'02 H'03 H'04 H'05 H'06 H'07 H'08 H'09 H'0A H'0B H'0C
Top raster to be displayed = 2
H'62 H'63 H'00 H'01
Figure 22 Vertical Scroll : 1/100Duty Cycle
26
Preliminary
Y-address H'00 H'01 H'02 H'03 H'04 H'05 H'06 H'07 H'08 H'09 H'0A
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HD66421
Top raster to be displayed = 0
H'4C H'4D H'4E H'4F Y-address H'01 H'02 H'03 H'04 H'05 H'06 H'07 H'08 H'09 H'0A H'0B
Top raster to be displayed = 1
H'4D H'4E H'4F H'50 Y-address H'02 H'03 H'04 H'05 H'06 H'07 H'08 H'09 H'0A H'0B H'0C
Top raster to be displayed = 2
H'4E H'4F H'50 H'51
Figure 23 Vertical Scroll : 1/80Duty Cycle
27
Preliminary
Partial Display Function The HD66421 can display only a part of a full display. The duty ratio of this partial display is 1/8 and rest of display is scanned with unselected levels. The position of this partial display can be located at any position with using partial display position register. To launch this mode, following processes are needed: (1) supplied voltage to VLCD must be cut off, PWR bit can be used if external voltage supplier is controlled with DCON output (R0) (2) set DTY bits (R1) (3) set display position (R11) (4) set contrast level (R16)
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HD66421
The clock frequency may be 220kHz at normal display mode. When a partial display is driven, oscillation frequency will be 18kHz, 1/12.5 of that of normal display mode. This function is useful for lower power dissipation. To change clock frequency, follow the process which is showed in Figure 28. Warning: VLCD must be cut off when partial display mode is launched. Vcc is supplied to LCD driving circuit instead of VLCD. So if VLCD is supplied externally during partial display mode, Vcc short-circuit to VLCD.
Table 6 Partial Display Block
R11 H'00 H'01 H'02 H'03 H'04 H'05 H'06 H'07 H'08 H'09 H'0A H'0B ADC= 0 COM1 -> COM9 -> COM17 -> COM25 -> COM33 -> COM41 -> COM100-> COM92 -> COM84 -> COM76 -> COM68 -> COM60 -> COM8 COM16 COM24 COM32 COM40 COM48 COM93 COM85 COM77 COM69 COM61 COM53 ADC= 1 COM8 COM16 COM24 COM32 COM40 COM48 COM93 COM85 COM77 COM69 COM61 COM53 -> -> -> -> -> -> -> -> -> -> -> -> COM1 COM9 COM17 COM25 COM33 COM41 COM100 COM92 COM84 COM76 COM68 COM60
Y address H'00 Display RAM Start line R5 R5+7 ABCD ABCD
LCD Panel
COM1 COM33 COM40 COM49,COM50 (Not used) COM100
R11=H'04
H'63
COM51,COM52 (Not used)
Figure 24 Partial Display
28
Preliminary
Blink Function The HD66421 can blink a specified area on the dot-matrix display. Blinking is achieved by repeatedly turning on and off the specified area at a frequency of one sixty-fourth the frame frequency. For example, when the frame frequency is 80 Hz. the area is turned on and off every 0.8 seconds. The area to be blinked can be designated by specifying vertical and horizontal positions of the area. The vertical position. or the rasters to be blinked, are specified by the blink start raster register (R6) and blink end raster register (R7).
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HD66421
The horizontal position, or the dots to be blinked in the specified rasters, are specified by the blink registers R8, R9 and R10 in an 8-dot group; each data bit in the blink registers controls its corresponding 8-dots group. The relationship between the registers and blink area is shown in figure 25. Setting the BLK bit to 1 in control register 2 after setting the above registers starts blinking the designated area. Note that since the area to be blinked is designated absolutely with respect to the display RAM, it will move along with a scrolling display (figure 26).
Blink start line (R6) Blink end line (R7)
SEG1 SEG9 SEG17 SEG25 SEG33 SEG41 SEG49 SEG57 SEG65 SEG73
LCD
00000011111000010001 Blink registers DDDDDDDDDDDDDDDDDDDD BBBBBBBBBBBBBBBBBBBB 76543210765432103210 Blink area
SEG81
SEG89
SEG97
SEG105
SEG113
SEG121
SEG129
SEG137
SEG145
SEG153
SEG160
R8
R9
R10
Figure 25 Blink Area Designation by Blink Control Registers
Display start raster = 0 Blink start raster = 0 Blink end raster = H'F
Display start raster = H'5 Blink start raster = H'5 Blink end raster = H'F
Figure 26 Scrolling Blink Area
29
Preliminary
Power Down Modes The HD66421 has a standby function providing low power-dissipation, which is initiated by internal register settings. During standby mode, all the HD66421 functions are inactive and data in the display RAM and internal registers except the DISP bit are retained. However, only control registers can be accessed during standby mode. HD66421 has an another power down mode: partial display. In this mode only a part of display
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HD66421
is active. However, this duty ratio is 1/8 so the external power supply for LCD drive will be inactive. The oscillator does not halt, thus dissipating more power than standby mode. Table 6 lists the LCD driver output pin status during standby mode. Figure 27 shows the procedure for initiating and canceling a standby mode and figure 28 shows the procedure for changing oscillator. Note that these procedure must be strictly followed to protect data in the display RAM.
Table 7 Output Pin Status during Power Down modes
Signal Name COM1-COM100 SEG1-SEG160 STBY 1 0 1 0 Status Output VLCD (display off) Output common signals (VLCD - GND) Output VLCD (display off) Output segment signals (VLCD - GND)
Oscillation halts OP amp power off External power supply off
Set STBY bit to 1 and AMP bit to 0 (control register 1) Standby mode Clear STBY and PWR bits to 0 and AMP bit to 1 (control register 1) Wait for oscillation and external power supply to stabilize Set DISP bit to 1 (control register 1)
Initiation
Oscillator starts OP amp power on Internal operation starts
Cancellation
Display starts
Figure 27 Procedure for Initiation and Canceling a Standby Mode
Set HOLT bit to 1 (control register 1) Set DTY or GRAY bit to 1 (control register 2) Wait for oscillation to stabilize Clear HOLT bit to 0 (control register 1)
Internal operation stops
Oscillator 2 starts working
Internal operation starts
Figure 28 Procedure for Changing Oscillator
30
Preliminary
Power On/Off Procedure
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HD66421
strictly followed to prevent incorrect display Figure 29 shows the procedure for turning the because the HD66421 incorporates a power power supply on and off. This procedure must be supply circuit.
Turn on power (power-on reset)
Set PWR,AMP bit to 1 (control register 1) Set CNF, ADC, DTY1, DTY0, INC bits according to the operating mode (control register1 and 2)
Boosting starts
Power on
Write data to registers and RAM as required
Set DISP bit to 1 (control register 1)
Clear DISP bit to 0 (control register 1) Power off
Clear PWR,AMP bit to 0 (control register 1)
Boosting halts
Turn off power
Figure 29 Procedure for Turning Power Supply On/Off
31
Preliminary
Oscillator The HD66421 incorporates two sets of R-C oscillator for two display modes: OSC-OSC1 oscillator is used for 32-levels gray scale display mode and OSC-OSC2 oscillator for 4-levels gray scale display mode. If the internal oscillator is not used, an appropriate clock signal must be externally input through the OSC pin. In this case, the OSC1 and OSC2 pins must be left unconnected. Oscillation resister must be placed near LSI, because if capacitance exists between OSC and OSC1 oscillator may not work properly. Figure 30 shows oscillator connections. Changing Oscillator Two oscillators are alternated automatically depending on modes. An external clock must be input from OSC terminal at any modes. Clock and Frame Frequency
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HD66421
The HD66421 generates the frame frequency by dividing the input clock. Clock frequency is determined with following equation: fOSC = N * (Duty ratio) * (Frame frequency) N: 31 for 32-level gray scale display mode 3 for 4-level gray scale display mode The frame frequency is usually 70 to 90 Hz; when the frame frequency is 70 Hz, for example, the input clock frequency will be 220 kHz for 32-level gray scale display mode, and 18kHz for 4-level gray scale. LCD Driving Alternating Cycle AC voltage needs to be applied to liquid crystals to prevent deterioration due to DC voltage. This alternated cycle is determied by setting Alernating cycle register (R16); 7, 11, 13lines or flame.
Clock
OSC HD66421 Rf2 Rf1
OSC HD66421 OSC1 OSC2 (Open) Rf
OSC HD66421 OSC1 OSC2
(Open) (Open)
OSC1 OSC2
a) External clock
b) Dual oscillator
c)Single oscillator
Figure 30 Oscillator Connections
Table 8 LCD alternative drive cycle
CM1 0 0 0 0 CM0 0 0 0 0 Alternative Cycle Frame 7 lines 11 lines 13 lines
32
Preliminary
Power Supply Circuits HD66421 has following circuits for power supply circuit: operational amplifiers, resistive dividers, bias control circuit and contrast control circuit. LCD driving voltage, VLCD, must be generated externally. LCD Drive Voltage Power Supply Levels: To drive the LCD, a 6-level power supply are necessary. These levels are generated internally or supplied from outside. When an internal voltage levels generator is chosen, external capacitors are needed to stabilize these levels. AS the HD66421 incorporates operational amplifiers to these levels, this circuit gives better quality of display with less power consumption. This divided ratio is programmable. Bias current of internal operational amplifier is determined with a resister which is inserted between IREFM and GND. This resister value is between 1M and 5M. Larger resister value make less power consumption at internal operational amplifier. However, too large value loose operational margin of amplifiers. Keep following relationship among voltage levels;
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HD66421
Contrast Control: Internal contrast control circuit can change the output voltage level of VLCD by setting data to contrast control register, R16. VLCD adjustable range are showed below; * 1/8 bias
0.73 * (VLCD-GND) VLCD 0.988 * (VLCD-GND)
* 1/9 bias
0.82 * (VLCD-GND) VLCD 0.993 * (VLCD-GND) (Example 1.)
* 1/11 bias
0.79 * (VLCD-GND) VLCD 0.992 * (VLCD-GND)
* Partial Display
0.82 * (Vcc-GND) VCC 0.997 * (VCC-GND) (Example 2.)
Partail display function uses 1/4 bias ratio from VCC to GND. 8 levels of contrast can be selected with data bit 2 to 0 of R16.
Vcc IREFMP > IREFM GND VLCD > Vcc > GREF GND VLCD V1O V2O V3O V4O V5O GREF GND VLCD-Vcc 1.0V IREFP-IREFM 1.0V Vcc-GREF 1.0V
Example.1 LCD bias level 1/80 duty Display(1/9 bias, VLCD=12V,GND=0V) 12 11 10 9 8 Voltage [V] 7 6 5 4 3 2 1 0 0 7 17 F Contrast (R16) 1F (maximum) 0 0 4 Contrast (R16) 7 (maximum) V3O V4O V5O 1 Voltage [V] 3 V4O 2 V5O VLCD V1O V2O V1O 4 V2O V3O Example 2. LCD bias level Partial Display(1/4 bias,VCC=5V,GND=0V) 5 VCC
33
Preliminary
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HD66421
LCD drive levels bias ratio: LCD driving levels External Power Supply Circuit: When the bias ratio can be selected from 1/8, 1/9, 1/10 or internal operational amplifier cannot fully drive 1/11. the LCD panel used, V1O to V5O voltages can be supplied from external power supply circuit. Power Supply: The HD66421 needs the external Here, the AMP bit must be set to 1 to turn off the power supply for LCD driving circuit. If this internal power supply circuit. power circuit has on/off control, the HD66421 controls the external power supply circuit by setting PWR bit.
External voltage booster
Vcc IREFP
VLCD
Operational amplifier OFF
VLCD
Vout C1 V1O on/off
r IV1 GND R4 IV2 IREFM Resister for bias current of operational amplifier r
R1 + R1 V2O R3 Bias control V3O R1 V4O R1 V5O R2 GREF DCON R1 = R R2 = 0.094R to 3R R3 = 4R to 7R R4 = 1M to 5M C1 = 1F to 3F C1 C1
+
C1
IV3 r
+
C1
IV4
+
r IV5 +
Contrast control circuit
resistive divider for partial display mode
HD66421
Figure 31
Power Supply Circuit
34
Preliminary
Reset
Rev. 1.1E '99.02.10
HD66421
Initial Setting of Pins: Bus interface pins The low RES signal initializes the HD66421, During reset, the bus interface pins do not accept clearing all the bits in the internal registers. During signals to access internal registers; data is reset. the internal registers cannot be accessed. undefined when read. LCD driver output pins During reset. all the LCD driver output pins (SEG1 to SEGl61, COM1 to COM100) output Vcc-level voltage, regardless of data value in the display RAM, turning off the LCD. Here, the output voltage is not alternated. Note that the Initial Setting of Internal Registers: All the same voltage (VLCD) is applied to both column internal register bits are cleared to 0. Details are and row output pins to prevent liquid crystals listed below. from degrading. - Normal operation - Oscillator is active; OSC-OSC1 is used - Display is off - Y address of display RAM is incremented - 1/100 duty cycle - X and Y addresses are 0 - Data in address H'0 is output from the SEGl pin - Blink function is inactive - Operational amplifier is disabled Note that if the reset conditions specified in the Electric Characteristics section are not satisfied, the HD66421 will not be correctly initialized. In this case, the internal registers of the HD66421 must be initialized by software.
35
Preliminary
Internal Registers The HD66421 has one index register and 18 data registers, all of which can be accessed asynchronously with the internal clock. All the registers except the display memory access register are write-only. Accessing unused bits or addresses affects nothing; unused bits should be set to 0 when written to. Index Register (IR): The index register (figure 32) selects one of 18 data registers. The index register itself is selected when both the CS and RS signals are low. Data bits 7 to 5 are unused; they should be set to 0 when written to. Control Register 1 (R0): Control register 1 (figure 33) controls general operations of the HD66421. Each bit has its own function as described below. RMW bit RMW = l: Read-modify-write mode Address is incremented only after write access RMW = 0: Address is incremented after both write and read accesses DISP bit DISP = 1: Display on DISP = 0: Display off (all LCD driver output pins output VLCD level)
Rev. 1.1E '99.02.10
HD66421
STBY bit STBY = l: Internal operation and oscillation halt; display off STBY = 0: Normal operation PWR bit PWR = l: Output high level from DCON terminal PWR = 0: Output low level from DCON terminal This bit controls the external power supply for LCD driving outputs. AMP bit AMP = 1: OP amp enable AMP = 0: OP amp disable REV bit REV = 1: Reverse display REV = 0: Normal display HOLT bit HOLT = l : Internal operation stops HOLT = 0: Internal operation starts ADC bit ADC = l: Data in X address H'0 is output from SEG160; row signals depend on duty. ADC = 0: Data in X address H'0 is output from SEG1; row signals are scanned from COM1.
Data bit Set value
7
6
5
4
3
2
1
0
Register number
Figure 32 Index Register (IR)
Data bit Set value
7
6
5
4
3 AMP
2 REV
1
0
RMW DISP
STBY PWR
HOLT ADC
Figure 33 Control Register 1 (R0)
36
Preliminary
Rev. 1.1E '99.02.10
HD66421
Control Register 2 (R1): Control register 2 The blink counter is reset when the BLK bit is set (figure 34) controls general operations of the to 0. It starts counting and at the same time HD66421. Each bit has its own function as initiates blinking when the BLK bit is set to l. described below. X Address Register (R2): The X address register BIS1, BIS0 bits (figure 35) designates the X address of the BIS1, 0 = (1, 1): 1/8 LCD drive levels bias ratio display RAM to be accessed by the MPU. The set BIS1, 0 = (1, 0): 1/9 LCD drive levels bias ratio value must range from H'00 to H'27 in the case of BIS1, 0 = (0, 1): 1/10 LCD drive levels bias ratio 8-bit a word or range from H'00 to H'35 in the BIS1, 0 = (0, 0): 1/11 LCD drive levels bias ratio case of 6-bit a word; setting a greater value is ignored. The set address is automatically WLS bit incremented each time the display RAM is WLS = l: A word length is 6-bits accessed; it is not necessary to update the address WLS = 0: A word length is 8-bits each time. Data bits 7 and 6 are unused; they should be set to 0 when written to. When you use GRAY bit monochrome display, the set value must range the GRAY = l : 4-levels of gray scale are fixed even number from H'00 to H'26 in the case of GRAY = 0: 4-levels of gray scale are selected 8-bit a word or range from H'00 to H'34 in the from 32-levels case of 6-bit a word. DTY1,DTY0 bits DTY1, 0 = (1, 1): 1/8 display duty cycle; partial display mode DTY1, 0 = (1, 0): 1/64 display duty cycle DTY1, 0 = (0, 1): 1/80 display duty cycle DTY1, 0 = (0, 0): 1/100 display duty cycle INC bit I NC = l: X address is incremented for each access INC = 0: Y address is incremented for each access BLK bit BLK = 1: Blink function is used BLK = 0: Blink function is not used
Data bit Set value 7 BIS1 6 BIS0 5 4 3 2 1 INC 0 BLK
Y Address Register (R3): The Y address register (figure 36) designates the Y address of the display RAM to be accessed by the MPU. The set value must range from H'00 to H'40; setting a greater value is ignored. The set address is automatically incremented each time the display RAM is accessed; it is not necessary to update the address each time. Data bit 7 is unused; it should be set to 0 when written to.
WLS GRAY DTY1 DTY0
Figure 34 Control Register 2 (R1)
Data bit Set value 7 6 5 XA5 4 XA4 3 XA3 2 XA2 1 XA1 0 XA0
Figure 35 X address Register (R2) Data bit Set value 7 6 5 4 3 2 1 0
YA6 YA5 YA4 YA3 YA2 YA1 YA0 Figure 36 Y address Register (R3)
37
Preliminary
Display Memory Access Register (R4): The display memory access register (figure 37) is used to access the display RAM. If this register is write-accessed, data is directly written to the display RAM. If this register is read-accessed, data is first latched to this register from the display RAM and sent out to the data bus on the next read; therefore, a dummy read access is necessary after setting the display RAM address. Display Start Raster Register (R5): The display start raster register (figure 38) designates the raster to be displayed at the top of the LCD panel. Varying the set value scrolls the display vertically. The set value must be one less than the actual top raster and less than the duty ratio. If the value is set outside these ranges, data may not be displayed correctly. Data bits 7 is unused; they should be set to 0 when written to.
Rev. 1.1E '99.02.10
HD66421
Blink Start Raster Register (R6): The blink start raster register (figure 39) designates the top raster in the area to be blinked. The set value must be one less than the actual top raster and less than the duty ratio. If the value is set outside these ranges, operations may not be correct. Data bits 7 is unused; they should be set to 0 when written to. Blink End Raster Register (R7): The blink end register (figure 40) designates the bottom raster in the area to be blinked. The area to be blinked is designated by the blink registers, blink start raster register, and blink end raster register. The set value must be one less than the actual bottom raster and less than the duty ratio. It must also be greater than the value set in the blink start raster register. If an inappropriate value is set, operations may not be correct. Data bits 7 is unused; they should be set to 0 when written to.
Data bit Set value
7 D7
6 D6
5 D5
4 D4
3 D3
2 D2
1 D1
0 D0
Figure 37 Display Memory Access Register (R4)
Data bit Set value
7
6 ST6
5 ST5
4 ST4
3 ST3
2 ST2
1 ST1
0 ST0
Figure 38 Display Start Raster register (R5)
Data bit Set value
7
6
5
4
3
2
1
0
BSL6 BSL5 BSL4 BSL3 BSL2 BSL1 BSL0
Figure 39 Blink Start Raster register (R6)
Data bit Set value
7
6
5
4
3
2
1
0
BEL6 BEL5 BEL4 BEL3 BEL2 BEL1 BEL0
Figure 40 Blink End Raster register (R7)
38
Preliminary
Blink Registers (R8 to R10): The blink bit registers (figure 41) designate the 8-bit groups to be blinked. Setting a bit to 1 blinks the corresponding 8-bit group. Any number of groups can be blinked; setting all the bits to 1 will blink the entire LCD panel. These bits are valid only when the BLK bit of control register 2 is 1. R10's data bits 7 to 4 are unused; they should be set to 0 when written to.
Rev. 1.1E '99.02.10
HD66421
Bit 4 is clock-enable bit. This bit sets to 1, the signal CO,CL1,FLM and M stop in master mode. They are high-Z. Data bits 7 and 5 are unused; they should be set to 0 when written to.
Gray Scale Palette Registers (R12 to R15): The gray scale palette registers (figure 43) designate the grayscale level or colour. Use these registers to enable an optimal grayscale or colour display. If GRAY bit is 1, these registers are inactive. Data Partial Display Block Register (R11): The Partial bits 7 to 5 are unused; they should be set to 0 display block register (figure 42) designates the when written to. block of partial display. It use from bit 3 to bit 0.
Data bit
7 BK0 BK8
6 BK1 BK9
5 BK2
4 BK3
3 BK4
2 BK5
1 BK6
0 BK7
R8 R9 R10
Set value Set value Set value
BK10 BK11 BK12 BK13 BK14 BK15 BK16 BK17 BK18 BK19
Figure 41 Blink Registers (R8, R9, R10)
Data bit Set value 7 6 5 4 CLE Row no. COM1 to COM8 COM9 to COM16 COM17 to COM24 COM25 to COM32 COM33 to COM40 COM41 to COM48 Set value H'06 H'07 H'08 H'09 H'0A H'0B 3 PB3 2 PB2 1 PB1 0 PB0
Set value H'00 H'01 H'02 H'03 H'04 H'05
Row no. COM100 to COM93 COM92 to COM85 COM84 to COM77 COM76 to COM69 COM68 to COM61 COM60 to COM53
(ADC= "0". If "1" , reverse direction)
Figure 42 Partial Display Start Raster Register (R11)
Data bit 7 6 5 4 3 2 1 0
R12 R13 R14 R15
Set value Set value Set value Set value
GP14 GP13 GP12 GP11 GP10 GP24 GP23 GP22 GP21 GP20 GP34 GP33 GP32 GP31 GP30 GP44 GP43 GP42 GP41 GP40
Figure 43 Grayscale Palette Registers (R12 to R15)
39
Preliminary
Contrast Control and LCD Alternative Drive Cycle Register (R16): The contrast control register (figure 44) designates the contrast level of LCD display. These bits change the voltage which is supplied to LCD drivers.
Rev. 1.1E '99.02.10
HD66421
The LCD alternative drive cycle register designates the number of lines that LCD drive outputs are alternated. Data bits 7 is unused; they should be set to 0 when written to.
Table 9 Grayscale Levels
GP14 GP24 GP34 GP44 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GP13 GP23 GP33 GP43 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GP12 GP22 GP32 GP42 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GP11 GP21 GP31 GP41 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GP10 GP20 GP30 GP40 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gray scale Level 0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31 GP14 GP24 GP34 GP44 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GP13 GP23 GP33 GP43 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GP12 GP22 GP32 GP42 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GP11 GP21 GP31 GP41 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GP10 GP20 GP30 GP40 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Gray scale Level 16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 1
Table 10 LCD alternative drive cycle
CM1 0 0 0 0 CM0 0 0 0 0 Alternative Cycle Frame 7 lines 11 lines 13 lines
Data bit Set value
7
6 CM1
5 CM0
4 CC4
3 CC3
2 CC2
1 CC1
0 CC0
Figure 44 Contrast Control register (R16)
40
Preliminary
Rev. 1.1E '99.02.10
HD66421
Figure 45 shows characteristics of the LCD effective value against grayscale. This value is almost linear at all grayscale range without LCD panel. This linearity will be lost if LCD panel is connected. In this case, the four appropriate levels must be selected from grayscale No.1 to 31. 2.4
VLCD=15V, Ta=25C, 1/9 bias
LCD Effective value [V]
2.3
LSI (No load)
2.2
R14(Default) LSI + LCDpanel R13(Default)
2.1
2.0
0
4
8
12
16
20
24
28
31
Grayscale No.
Figure 45 LCD Effective Value
41
Preliminary
Plane Selection Register (R17): The plane selection register (figure 46) controls general operations of the HD66421. Each bit has its own function as described below. MON bit MON = l: Monochrome display MON = 0: 4-level gray scale display
Rev. 1.1E '99.02.10
HD66421
DSEL bit DESL = 1: Plane 1 is displayed DESL = 0: Plane 0 is displayed PSEL bit PESL = 1: Access to plane 1 from CPU PESL = 0: Access to plane 0 from CPU
Data bit Set value
7
6
5
4
3
2 MON
1
0
DSEL PSEL
Figure 46 Plane Selection Register (R17)
Note
When you use the monochrome display, you have to initialize the x-address to even number before access to display RAM. And you alway have to use even number.
42
Preliminary
Absolute Maximum Ratings
Item Power supply Logic circuit voltage LCD drive circuit Input voltage 1 Input voltage 2 Operating temperature Storage temperature Notes: 1 2 3 4 Symbol Vcc VLCD VT1 VT2 Topr Tstg Ratings -0.3 to +7.0 -0.3 to +20.0 -0.3 to Vcc+0.3 -0.3 to VLCD+0.3 -40 to +85 -55 to +110 Unit V V V V C C
Rev. 1.1E '99.02.10
HD66421
Notes 1 1, 2 1, 3
.Measured relative to GND Applies to pins M/S, OSC, OSC1, OSC2, DB7 to DB0, RD, WR, CS, RS, RES, CL1, M, FLM Applies to pins V1O, V2O, V3O, V4O and V5O If the LSI is used beyond its absolute maximum rating, it may be permanently damaged. It should always be used within the limits of its electrical characteristics to prevent malfunction or unreliability.
43
Preliminary
Electrical Characteristics
Rev. 1.1E '99.02.10
HD66421
DC Characteristics (Vcc=2.2 to 5.5V, GND=0V, VLCD=6 to 18V, Ta=-40 to +85C Note 9) Applicable Item Symbol Pins min. I/O leakage IIOL -1 current V-pins leakage IVL -10 current SEG1 to SEG160 Driver on Ron COM1 to COM100 resistance Input high 0.8xVcc VIH1 voltage Input low 0 VIL1 voltage Output high VOH DB7 to DB0 0.8xVcc voltage Output low VOL DB7 to DB0 0 voltage Current consumption Idisp Vcc during display Current consumption during standby Current consumption in LCD drive part Istb Vcc Typ Max 1 10 20 Vcc 0.2xVcc Vcc 0.2xVcc T.B.D Unit A A k V V V V A IoH=-50A IoL=50A Vcc = 3.0V Rf = 180k Measurement Condition Vin=Vcc to GND Vin=GND to VLCD Ion = 100A VLCD = 6V Notes 1 2 3 1 1 4 4 5, 6
1
5
A
5, 7
Ilcd
VLCD
T.B.D
A
5, 8
Notes: 1 Applies to pins: M/S, CS, RS, WR, RD, RES, OSC, DB7 to DB0, CL1, M and FLM 2 Applies to pins: V0O, V1O, V2O, V3O, V4O and V5O 3 Indicates the resistance between one pin from SEG1 to SEG160,COM1 to COM100 from V1O to V5O V1O and V2O should be near VLCD level, and V3O to V5O should be near GND level. All voltage must be within V.V is the range within which Ron is stable. V1 to V4 levels should keep following condition:VLCDV1OV2OV3OV4OV5OGND 4 Applies to pins: DB7-DB0, CO, CL1, M and FLM 5 Input and output current are excluded. When a CMOS input is floating, excess current flows from power supply to the input circuit. To avoid this, ViH and ViL must be held to Vcc and GND levels, respectively. The current which flows at resistive divider and LCD are excluded. Where the unmolded side of LSI is exposed to light , excess current flows. Use under sealed condition. 6 Specified under following conditions: Internal oscillator is used; Rf = 180k 32-levels gray scale mode; GRAY = 0 CO,CL1,FLM,M stop; CLE = 1 Vcc = 3.0V Checker board is displayed No access fro CPU 7 Measured during stand-by mode. Vcc = 3.0V 8 Specified under following conditions: Internal power supply circuit is used. Resister value is 5M which is connected between IREFM and GND Vcc = 3.0V, VLCD = 15V, IREFP = Vcc, GREF = GND All electrical characteristic are guaranteed at +85C for die products. 9.
44
Preliminary
Input Terminal Pins: CS, RS, WR, RD, RES, M/S Output Terminal Pins: CO
Rev. 1.1E '99.02.10
HD66421
M/S CO data
I/O Terminal
Pins: DB7 to DB0, FLM, M, CL1
Input Enable
Output Enable Data
Figure 47 Terminal Configuration
45
Preliminary
AC Characteristics (Vcc = 2.2 to 5.5V, GND = 0V, Ta = -40 to +85C
Clock Characteristics Item Oscillation frequency External clock frequency External clock duty cycle External clock fall time External clock rise time MPU Interface Item RD low-level width RD high-level width WR low-level width WR high-level width Address setup time Address hold time Data delay time Data output hold time Data setup time Data hold time Symbol tWRDL tWRDH tWWRL tWWRH tAS tAH tDDR tDHR tDSW tDHW Min 250 190 450 250 190 450 20 20 - - 20 150 100 10 Typ - - - - - - - - - - - - - - Max 4tOSC - 450 4tOSC - 450 - 4tOSC - 450 4tOSC - 450 - - - 180 150 - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Symbol fOSC fCP Duty tr tf Min 160 50 45 - - Typ 220 - 50 - - Max 280 400 55 0.2 0.2 Unit kHz kHz %
Rev. 1.1E '99.02.10
HD66421
Note 1)
Notes Rf = 180k, Vcc = 3.0V
s s
Notes Vcc = 2.2V to 3.0V, 2 Vcc = 3.0V to 5.5V, 2 Vcc = 2.2V to 3.0V, 2 Vcc = 3.0V to 5.5V, 2
Vcc = 2.2V to 3.0V Vcc = 3.0V to 5.5V Vcc = 2.2V to 3.0V Vcc = 3.0V to 5.5V
Reset Timing Item Symbol Min Typ Max Unit RES low-level width tRES 1 - - ms Note 1 All electrical characteristic are guaranteed at +85C for die products. Note 2 tOSC = 1 / fOSC
Notes
tWRDL
RD
tWRDH tWWRH tWWRL tAS tDSW tAH
WR
tAS
tAH
RS,CS DB7DB0
tDDR
tDHR
Figure 44 MPU Interface
tDHW
Notes. The following load circuit is connected for specification. VOH and VOL of the timing specification is 1/2 VCC level. Output terminal 30pF(includes board capacitance)
46

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